Hello! I'm Parsa Mirfasihi

As a passionate VLSI and hardware design enthusiast, I specialize in developing efficient and high-performance hardware solutions with a strong focus on innovation and reliability. My expertise spans the complete ASIC workflow and RTL-to-GDSII flow, including physical design, digital design verification, FPGA-based system design, low-power optimization, SRAM circuit design, and static timing analysis. Proficient in industry-standard Synopsys and Cadence tools, I excel at optimizing circuits for speed, power, and area while ensuring robust hardware security. In addition to my hardware expertise, I leverage Python to develop automation scripts and verification frameworks, enhancing design validation and streamlining workflows. With strong proficiency in SystemVerilog and advanced verification methodologies, I continuously push the boundaries of next-generation semiconductor technologies and hardware optimization.

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Years Experience

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Projects Completed

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Publications

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Experience

September 2024- April 2025 Energy Engineer

Industrial Assessment Center

Supported the DOE-funded Industrial Assessment Center (IAC) at San Francisco State University.
Delivered no-cost, professional energy-efficiency assessments to industrial and manufacturing facilities.
Conducted on-site inspections and data collection.
Performed engineering analyses of energy use, electrical loads, water consumption, and waste generation.
Identified opportunities: ECOs, WMOs, WCOs, PIOs, RGOs, and Cogeneration.
Produced a confidential report within two months including utility rate structures, energy breakdowns, and tailored recommendations supported by technical and economic analysis.
Drove sustainable industrial practices through actionable, engineering-driven solutions.

January 2025 - Present Graduate Research Assistant

Nano-Electronics & Computing Research Lab

Built an ML-driven framework to automatically choose the best equivalent model—Lumped-C, RC, Pi, Double-Pi—for distributed RC networks.
Integrated Python automation with SPICE to extract propagation delay, slew, and tail behavior under varying R, C, and segmentation.
Implemented a driving-point admittance propagation algorithm to generate reduced-order interconnect models.
Benchmarked reduced models against full RC tree simulations, achieving < 5% delay error.
Performed extensive transient and parametric sweeps in HSPICE to validate accuracy and flag cases requiring higher-order representations.
Result: faster interconnect modeling and improved timing analysis across accuracy, scalability, and speed.

Part-time Teaching Assistant

San Francisco State University

Digital Design System / Laboratory
Control Systems
Computer Systems
Linear System Analysis
Operational Amplifier System Design
Communication Systems

Education

2024-2026 Master of Science in Electrical and Computer Engineering

San Francisco State University

2017-2022 Bachelor of Science in Electrical and Electronics Engineering

Iran University of Science and Technology

Projects

Custom SRAM Design in 14nm CMOS Technology

Designed a 16×18 SRAM architecture from scratch using a 14nm PDK in Synopsys Custom Compiler, focusing on area optimization, access time, and power efficiency. Implemented and verified key circuits including the precharge unit, write driver, sense amplifier, address decoder, and SRAM cell array, ensuring robust read/write functionality and signal integrity under worst-case operating conditions. Conducted comprehensive functional verification and power characterization using structured read/write test sequences in Custom Compiler and WaveView. Validated design integrity by clearing DRC and LVS checks, confirming compliance with design rules and layout-versus-schematic consistency.

A Real-Time Intelligent Framework for Automated Object Recognition and Classification

This project focused on the design and implementation of a real-time intelligent system for object detection and classification in autonomous vehicles, leveraging deep learning and computer vision to enhance driving safety and efficiency. The system was implemented using TensorFlow on an NVIDIA Quadro 1000P GPU, enabling GPU-accelerated processing for real-time performance. Advanced architectures such as SSD, Faster R-CNN, and Mask R-CNN were evaluated on the MS COCO dataset, where the system achieved 21 FPS with SSD + InceptionV2 for high-speed detection and 88% mAP with Mask R-CNN for high-accuracy classification. The work demonstrates the potential of vision-based AI systems as scalable and cost-effective alternatives to sensor-heavy approaches in autonomous driving and related intelligent applications.

Teradyne J750 Semiconductor Test System Training & Setup

Collaborated with Teradyne experts during the on-campus installation of the J750 semiconductor test system at the Nano Electronics & Computing Research Laboratory (SFSU). Completed extensive hands-on training covering test procedures, system configuration, hardware/software integration, and IG-XL software development for device testing. Assisted with initial system calibration and conducted scan test, ADC, and DAC test development to validate device functionality. Authored a comprehensive technical report documenting the J750’s specifications, capabilities, and setup process—establishing a reference guide for future lab users.

ASIC Implementation of Motion Estimator in 14nm FinFET Technology

Designed and implemented a motion estimator for video compression using the Block-Matching Algorithm, with a 16×16 reference block and a 32×32 search block. Developed Verilog modules including Processing Elements, Comparator, and Controller, organized in a pipelined architecture for high throughput. Completed the full RTL-to-GDSII flow, covering front-end synthesis, static timing analysis, and back-end physical design. Performed area and power optimization, ECO-based hold violation correction, and physical verification with DRC to ensure layout sign-off. This project reinforced expertise in ASIC design, physical implementation, and advanced node technology (14nm FinFET).

DFT-Oriented PCB for Power and Signal Integrity Validation of Mixed-Signal SoC using Teradyne J750

Designed a custom PCB to support Design-for-Test (DFT) validation of a mixed-signal SoC, focusing on power delivery network (PDN) stability, clock distribution, and high-speed signal integrity. The board incorporated decoupling capacitor networks, controlled impedance traces, analog test access points, and boundary-scan hooks to monitor IR drop, voltage ripple, jitter, and crosstalk across digital and analog domains. Leveraged the Teradyne J750 Automated Test Equipment (ATE) to apply functional and parametric test vectors, measure delay and noise margins, and characterize analog/digital interactions under test stress conditions. This work enhanced expertise in mixed-signal PCB design, DFT methodologies, and ATE-based validation, bridging SoC test strategy with practical hardware implementation.

Skills

Verilog

Python

UVM

TCL

C/C++

Perl

STA

Synopsys
EDA

LangChain

Linux/Unix

VHDL

Machine
Learning

PCB Design

Contact Me

Get In Touch

Feel free to reach out to me for collaboration opportunities or any questions you may have.

Parsa Mirfasihi
mirfasihiparsa@gmail.com