Hello! I'm Parsa Mirfasihi

I am a Ph.D. student in Electrical and Computer Engineering at the University of Arizona, with hands-on experience in ASIC design, physical design, and verification. My background spans the full VLSI design flow, including RTL development, SystemVerilog-based verification, physical implementation, timing analysis, and Python-driven design automation. My current research focuses on hardware Trojans, hardware security vulnerabilities, agentic AI/LLMs, and transformer-based models for secure and intelligent hardware systems. I am particularly interested in the intersection of VLSI design, hardware security, and AI-assisted design methodologies. I am currently seeking internship or co-op opportunities in hardware design, physical design, verification, hardware security, or application engineering, where I can contribute my technical skills, research experience, and strong foundation in digital design and automation.

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Years Experience

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Projects Completed

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Publications

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Experience

Jan 2025 — Present

Graduate Research Assistant

PRISM-LAB

Tucson, AZ

Privacy-preserving, Intelligent, and Secure Computing Lab

Co-authored and presented a paper titled "Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection" accepeted for IEEE VLSI Test Symposium 2026. Can Agents Secure Hardware?
Co-authored a paper titled "LeakSEAL: Power Side-Channel Leakage Analysis and Mitigation for Secure Edge AI Learning" submitted to GLSVLSI 2026.
Authored a paper titled "FedLLM4HW: Carbon-Aware Federated Triage of Hardware Weaknesses in LLM-Generated Verilog Code" submitted to IGSC 2026.

Jan 2025 — May 2026

Graduate Research Assistant

NECRL

San Francisco, CA

Nano-Electronics & Computing Research Lab

Research on machine learning–driven modeling and optimization of VLSI interconnects to improve timing accuracy and design scalability.

Designed a data-driven framework to select optimal RC equivalent models (Lumped-C, π, double-π, distributed) for gate-delay estimation, achieving under 1% deviation versus fully distributed models.
Implemented an automated Python–SPICE workflow for timing extraction and reduced-order model generation using driving-point admittance propagation.
Validated the approach on 10,000 randomized RC networks: achieved up to 98% classification accuracy for propagation delay and 96% for transition time, confirmed by HSPICE transient analysis.
Improved timing-closure efficiency and scalability for large IC designs through adaptive ML-based modeling.
This work has been accepted as work-in-progress (WIP) at Design Automation Conference (2026).

Sep 2024 — Apr 2025

System-Level Power Analysis Engineering Intern

Industrial Assessment Center

San Francisco State University

Industrial Assessment Center

Led DOE-funded energy audits focused on electrical systems and system-level power analysis.

Served as audit lead for multiple on-site assessments, overseeing electrical metering, instrumentation, and data validation.
Collected and analyzed high-resolution electrical power/load datasets; performed statistical analysis and feature extraction using Python and R.
Developed system-level power models to identify peak drivers and estimate energy and cost savings.
Prepared and co-authored concise technical reports and presentation materials with the project team for client stakeholders and incentive submissions.

January 2024 — May 2026

Teaching Assistant

Department of Electrical and Computer Engineering

San Francisco State University

Digital Design System / Laboratory
Introduction to Microcontrollers
Control Systems
Computer Systems
Linear System Analysis
Operational Amplifier System Design
Communication Systems
Systems Dynamics and Mechanical Vibrations

Education

August 2026

University of Arizona

Doctor of Philosophy in Electrical and Computer Engineering

Key courses: Reconfigurable Computing, Web Development Internet of Things, Quantum Sensing and ML

January 2024 — May 2026

San Francisco State University

Master of Science in Electrical and Computer Engineering

Key courses: Advanced Digital Design, Digital VLSI Design, Analog IC Design, Digital Design Verification

GPA: 4.0 / 4.0

September 2017 — May 2022

Iran University of Science and Technology

Bachelor of Science in Electrical Engineering

GPA: 3.8 / 4.0

Projects

Custom SRAM Design in 14nm CMOS Technology

Designed a 16×18 SRAM architecture from scratch using a 14nm PDK in Synopsys Custom Compiler, focusing on area optimization, access time, and power efficiency. Implemented and verified key circuits including the precharge unit, write driver, sense amplifier, address decoder, and SRAM cell array, ensuring robust read/write functionality and signal integrity under worst-case operating conditions. Conducted comprehensive functional verification and power characterization using structured read/write test sequences in Custom Compiler and WaveView. Validated design integrity by clearing DRC and LVS checks, confirming compliance with design rules and layout-versus-schematic consistency.

A Real-Time Intelligent Framework for Automated Object Recognition and Classification

This project focused on the design and implementation of a real-time intelligent system for object detection and classification in autonomous vehicles, leveraging deep learning and computer vision to enhance driving safety and efficiency. The system was implemented using TensorFlow on an NVIDIA Quadro 1000P GPU, enabling GPU-accelerated processing for real-time performance. Advanced architectures such as SSD, Faster R-CNN, and Mask R-CNN were evaluated on the MS COCO dataset, where the system achieved 21 FPS with SSD + InceptionV2 for high-speed detection and 88% mAP with Mask R-CNN for high-accuracy classification. The work demonstrates the potential of vision-based AI systems as scalable and cost-effective alternatives to sensor-heavy approaches in autonomous driving and related intelligent applications.

Teradyne J750 Semiconductor Test System Training & Setup

Collaborated with Teradyne experts during the on-campus installation of the J750 semiconductor test system at the Nano Electronics & Computing Research Laboratory (SFSU). Completed extensive hands-on training covering test procedures, system configuration, hardware/software integration, and IG-XL software development for device testing. Assisted with initial system calibration and conducted scan test, ADC, and DAC test development to validate device functionality. Authored a comprehensive technical report documenting the J750’s specifications, capabilities, and setup process—establishing a reference guide for future lab users.

ASIC Implementation of Motion Estimator in 14nm FinFET Technology

Designed and implemented a motion estimator for video compression using the Block-Matching Algorithm, with a 16×16 reference block and a 32×32 search block. Developed Verilog modules including Processing Elements, Comparator, and Controller, organized in a pipelined architecture for high throughput. Completed the full RTL-to-GDSII flow, covering front-end synthesis, static timing analysis, and back-end physical design. Performed area and power optimization, ECO-based hold violation correction, and physical verification with DRC to ensure layout sign-off. This project reinforced expertise in ASIC design, physical implementation, and advanced node technology (14nm FinFET).

Skills

Verilog

Python

UVM

TCL

C/C++

Perl

STA

Synopsys
EDA

LangChain

Linux/Unix

VHDL

Machine
Learning

PCB Design

Contact Me

Get In Touch

Feel free to reach out to me for collaboration opportunities or any questions you may have.

Parsa Mirfasihi
mirfasihiparsaa@gmail.com